1. Field of the Invention
The present invention relates to a disk cache management method of a disk array device and, more particularly, to a disk cache management method of a disk array device mounted with a plurality of host directors (also called host adaptor) and a memory serving as a disk cache shared by these host directors (hereinafter referred to as shared memory).
2. Description of the Related Art
A disk array device mounted with a plurality of host directors in general has a shared memory of a large capacity mounted thereon for use as a disk cache. When a read command received from a host computer (hereinafter simply referred to as host) hits the cache, data can be transferred to the host without mechanical operation of a physical disk, so that a rapid response is possible. Also when receiving a write command, a fast response is enabled by ending the write command at a time when data is written to the disk cache and then writing the data to the physical disk later.
The above-described conventional technique, however, only has a rapid response as compared with mechanical operation of a physical disk and depending on a load on an application of a host, a faster response might be demanded.
Out of a response time required at the time of cache hit, one of elements peculiar to a disk array device mounted with a plurality of host directors and a shared memory is a cache page exclusive processing time. When receiving a read/write command from the host, the host director conducts cache page opening processing prior to data transmission and reception. This processing is to conduct exclusive control of the cache page in question during data transmission and reception to prevent another host, director or other task processing of the host director in question from accessing the same cache page or conducting processing of purging a cache page in use. Conversely, after data transfer is completed, it is necessary to conduct closing processing of the cache page in question in order to make the cache page be accessible by another host director or other task processing of the host director in question and be a target of LRU (Least Recently Used) control.
Opening processing and closing processing of a cache page are conducted by updating cache management information on a shared memory. While time for accessing the shared memory should be inevitably increased in hardware as the disk array device is increased in scale to have the number of host directors and the capacity of the shared memory increased, port performance and director performance improve rapidly, so that the processing is relatively bottlenecking performance. As a result, in command processing at the time of cache hit, time required for cache page opening processing and closing processing is too long to be negligible.
Among related conventional art is Japanese Patent Laying-Open (Kokai) No. 2000-267815. “Disk Array Controller” disclosed in the literature includes a plurality of units as an interface with a host computer/a disk device, duplexed shared memory units each one-to-one connected to each interface unit through an access path, a selector connected to the plurality of interface units and a cache memory connected to the selector, in which with the number of access paths between the plurality of interface units and the selector set to be more than the number of access paths between the cache memory and the selector, processors of the plurality of interface units conduct double write to the duplexed shared memory unit. The conventional art, however, fundamentally differs from the present invention in structure and function in that a local memory fails to have a local search table, a local management information entry and the like.